1. Field of the Invention
The present invention relates to an output buffer circuit having a so-called pre-emphasis function of emphasizing a signal waveform according to attenuation of a transmission line in data transmission at an information processing device or the like and, more particularly, an output buffer circuit having a high-speed output pre-emphasis function which realizes low power, low voltage and low noise.
2. Description of the Related Art
Output buffer circuits having a pre-emphasis function of this kind have been conventionally used particularly in data transmission as output circuits which require long-distance transmission, low voltage and high-speed (high-frequency) operation.
Although the output buffer circuit of this kind is realized in general by a current mode type circuit (circuit handling a signal expressed by the amount of current), the current mode type circuit has a shortcoming that it has a disadvantage in operation at a low power supply voltage because of its structure. With the recent advance of semiconductor integrated circuit microfabrication techniques, however, lower power consumption has been realized by the reduction in an operation voltage to demand operation at a higher speed with a lower power supply voltage.
Proposed as a conventional technique meeting such a demand is the circuit realizing high-speed operation by shortening a propagation delay time from an input unit to an output unit while operating at a low power supply voltage, which is disclosed in Japanese Patent Laying-Open (Kokai) No. 2002-94365. Also proposed is the technique of improving an output buffer circuit operable with low power which is disclosed in Japanese Patent Laying-Open (Kokai) No. 2000-68816.
Among the above-described conventional techniques, the output buffer circuit disclosed in Japanese Patent Laying-Open (Kokai) No. 2002-94365, for example, has a shortcoming that a lack of mechanism of cutting off current when the pre-emphasis function is disabled (at the time of de-pre-emphasis) makes current fluctuate largely, which is not suitable for low power consumption.
Another shortcoming is that due to large current fluctuation, noise is liable to be generated, which is a disadvantage in high-speed transmission.
Since according to the present invention, control circuits (B1 to B4) need to conduct none of such complicated logical operation as a logical product (AND) and a logical sum (OR) by using data to be sent and an output buffer circuit is formed by two stages of inverters from an input unit (TA, TB) to an output unit (SOUT), a delay time is equivalent to that of the output buffer circuit disclosed in Japanese Patent Laying-Open (Kokai) No. 2002-94365 and higher-speed operation than that of the output buffer circuit disclosed in Japanese Patent Laying-Open (Kokai) No. 2000-68816 is possible.